1. Field of the Invention
The present invention relates generally to a multilayer conductive wire for semiconductor device formed of two or more conductive layers, and more specifically, to a highly reliable multilayer conductive wire free from stress migration and without losing conductivity.
2. Description of the Background Art
The background art will be described in conjunction with the drawings.
A conventional multilayer conductive wire is, for example, of a three-layer structure as shown in FIG. 16 (Japanese Patent Laying-Open No. 2-186634, etc.). Referring to FIG. 16, the conventional multilayer conductive wire is formed of a barrier metal layer 1 formed of a metal such as TiN and TiW having a thickness of about 1000.ANG., an aluminum alloy layer 2 of, for example, Al--Si--Cu, and Al--Cu, with a thickness in the range between 5000.ANG. and 10000.ANG. formed on its surface by sputtering, and a metal layer 3 of, for example, Ti, Mo, W with a thickness of about 1000.ANG. formed on the surface thereof by sputtering, etc., on which an interlayer insulating film (not shown) is formed.
Such a multilayer conductive wire is mainly used for a conductive wire tolerating a large current and needed to have its width reduced such as a power supply wire for, for example, an LSI (Large Scale Integrated Circuit).
Metal layer 3 formed of metal such as Ti is formed on the surface of aluminum alloy layer 2 to form a three-layer structure, because a wire of two-layer structure without the layer overlying aluminum alloy layer 2 in other words without metal layer 3 is encountered with the following problem when an interlayer insulating film is directly formed on the surface thereof.
As shown in FIG. 19, suppose that a conductive wire 43 formed of an aluminum alloy is formed covering the surface of a stepped portion produced in the formation of an insulating layer 42 on a silicon substrate 41, and an interlayer insulating film 44 of SiO.sub.2 is further formed thereon. When the structure is supplied with a resist film 45 of positive type in order to form a via hole in interlayer insulating film 44 at the upper part of the stepped portion and is subjected to photolithography, light transmitted through resist film 45 and interlayer insulating film 44 at the time of exposure reflects irregularly as indicated by the arrows B and C upon the surface of conductive wire 43 which is highly reflective. As a result, when an opening 46 having a width represented by the double dotted chain is formed, the resist is excessively developed as far as the position 46a shown by the broken line and removed away. Consequently, the region of interlayer insulating film 44 to be subsequently etched becomes larger than the area of the opening of a desired via hole. This is a so-called notching phenomenon. Conversely, as shown in FIG. 16, formation of metal layer 3 such as Ti having lower light reflectivity than aluminum alloy on aluminum alloy layer 2 prevents the notching phenomenon due to the reflection of the light upon the exposure in the process of photolithography.
Also, when an insulating film of, for example, SiO.sub.2 is deposited on the conductive wire with the surface of aluminum alloy layer exposed thereon and a via hole is formed therein, especially in the case of a DRAM (Dynamic Random Access Memory) of a megabit class, about several ten% overetching is necessary in forming a via hole of submicron level. The overetching is conducted with the surface of aluminum alloy layer at the bottom of the via hole being exposed, a polymer is synthesized by the aluminum alloy, resist and a plasma containing a gas etching an oxide film. The polymer sticking to the inner wall of the via hole often gives rise to a disconnection of a conductive wire in connecting the same through the via hole in a succeeding process or results in poor coverage.
Referring to FIGS. 17A to 17D, a description will be provided on the mechanism of the disconnection of a conductive wire in connecting the same in the via hole due to the synthesization of the polymer.
Referring to FIG. 17A, when a silicon oxide film 32 is formed on an aluminum alloy wire layer 31 formed on an insulting layer 30 by means of CVD (Chemical Vapor Deposition), a resist film 33 with an opening 34 is formed, and then etching is conducted in order to form a via hole 35 in silicon oxide film 32, three condition for the aluminum alloy, resist and a gas for etching oxide film are satisfied while aluminum alloy conductive layer 31 is overetched, and, therefore, a polymer 36 is deposited on the inner walls of via hole 35 and opening 34. The upper end portion of polymer 36 remains as shown in FIG. 17C after resist film 33 is removed away. Therefore, deposition of conductive metal layers 37a and 37b such as aluminum for wire connection with aluminum alloy layer 31 by means of sputtering in via hole 35 causes conductive metal layers 37a and 37b cut off by the presence of polymer 36, thereby rendering the layers disconnected.
A problem due to a polymer as stated above will not arise in the case of multilayer conductive wire shown in FIG. 16, because the overetching is not conducted with the surface of aluminum alloy layer 2 being exposed.
However, a conventional multilayer conductive wire as shown in FIG. 16 is still encountered with the following problem.
When a conventional multilayer conductive wire as shown in FIG. 16 is disposed covered with a passivation film in the periphery of a semiconductor device region formed on a rectangular semiconductor chip, sealing thereon with further resin causes strong stress to be concentrated on the four corners of the periphery of the chip due to the difference, etc. in the amounts of shrinkage by dehydration between the mold resin and the passivation film at the time of heat-treatment. Therefore, cracks are produced in the passivation film at those positions, and sliding is caused between the joint of the layers of multilayer conductive wire, thereby destroying the wire.
The cause for this sliding phenomenon between the layers will be described in conjunction with FIG. 21. A cross section shown in FIG. 21 is formed by providing a passivation film 81 on the conventional multilayer conductive wire shown in FIG. 16 and by further covering the same with mold 82. At the interface S1 between mold 82 and passivation film 81, when the difference in the amounts of heat shrinkage at the time of heat-treatment is large between mold 82 and passivation film 81, sliding takes place due the stress caused by the difference. When no sliding takes place at the interface S1 and the difference in the heat-shrinkage amounts between passivation film 81 and the metal layer 3 is relatively large, sliding takes place at the interface S2. In this case, sliding sometimes takes place at interface S3 or interface S4 not at interface S2. Also, at interfaces S3 and S4, sliding sometimes takes place due to the difference in the degrees of temperature rising at the time of conduction caused by the difference in electrical resistance between metal layer 3 and aluminum alloy layer 2 or between aluminum alloy layer 2 and barrier metal 1.
It has been demonstrated by experiments that cracks are likely to be formed in the passivation film at the upper portion of a conductive wire or its periphery and the larger the width of the conductive wire, the more frequent cracks are formed. This is because the passivation film and the mold resin greatly shrink by dehydration, etc. in accordance with heat-treatment, while aluminum alloy, etc. is not deformed very much, and, therefore force due to the stress would act upon these interfaces, the force increasing as a function of the area of these interfaces.
One approach directed to solution of such a problem due to application of stress into the periphery of a chip is disclosed, for example, in Japanese Patent Laying-Open No. 57-45259. The semiconductor device disclosed in the document, referring to FIGS. 18A and 18B, includes a semiconductor element region 13 formed on a silicon substrate 11 of a first conductivity type and having its elements isolated by a field insulating film 12. The surface of semiconductor element region 13 is covered with a thin first surface insulating film 14, and the surfaces of first surface insulating film 14 and field insulating film 12 are further covered with a second surface insulating film 15. Provided on the surface of second surface insulating film 15 are an aluminum wire 16, a bonding pad 17, and a guard ring 18. Aluminum wire 16 comes into ohmic contact with semiconductor element region 13 in a through hole 19 formed in the first and second surface insulating films 14 and 15. Guard ring 18 of a aluminum film is formed along the periphery of silicon substrate 11, and when connected to a ground terminal, prevents an inversion layer from being formed. A slit 20 is provided at a corner of guard ring 18, and the effect of stress concentration is relaxed at the corner, because the width of guard ring 18 is reduced by the width of slit 20. Consequently, formation of cracks in passivation film 21 can be restrained.
However, when a slit is formed in a conductive wire in the periphery of a chip by applying the above-stated conventional technique, the cross-sectional area of the conductive wire at that position is reduced by the area of the slit, so that electrical resistance as the conductive wire increases in proportion to the reduction. In Conductor portions on the opposing sides of the slit (FIG. 18A), conductive wire portions (18a and 18b) extending in parallel with guard ring 18 at the position where the slit 20 is formed has an outer portion (conductive wire portion 18a in FIG. 18A) significantly longer than its inner portion (conductive wire portion 18b in FIG. 18A) even with the cross-sectional widths being identical. Therefore, with difference being generated in the resistance values of these portions, and, therefore the distribution of joule heat when current flows therethrough will be different. Local heat-stress takes place due to the uneven temperature distribution, thereby disconnecting the wires.